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James Kress

Variable Sequence Detector and Display Module ~ Spring 2011

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This was the final project for Digital Systems Lab. We had to design a system on an FPGA that would listen for its address to be sent, and then act upon the data. The lab report and the pictorial user guide of the FPGA are available to be downloaded.

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user_guide.pdf
File Size: 2489 kb
File Type: pdf
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lab_final_report.pdf
File Size: 257 kb
File Type: pdf
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