Pipelined Processor ~ Spring 2012
Data Path for the Processor
Part 1: Register FileThe first stage was to create the register file that would be used to store the working data for the processor. This was implemented in Xilinx, and tested using ModelSim.
The description for the register file is provided in the 'part01_reg_file.pdf' file. It gives a description of the needed functionality and naming conventions. The final report is given as 'group17_part1_report.pdf'. This file gives a description of our design process, the design schematic, and a rundown of our testing methods. |
Part 1 Files
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Part 2: AdderThe second stage of the project was to create a high performance 16-bit 2's compliment adder. To improve code readability and reusability, we created the adder in three parts. First, we created a single-bit adder. This adder was then instantiated four times to create the four-bit adder, which was then instantiated four times itself, to create the 16-bit adder.
The description for the adder is provided in the 'part02_adder.pdf' file. It gives a description of the needed functionality and naming conventions. The final report is given as 'group17_part02_report.pdf'. This file gives a description of our design process, the design schematic, and a rundown of our testing methods. |
Part 2 Files
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Part 3: ALUThe third stage of the project was the create the ALU (Arithmetic Logic Unit). The ALU has the ability to perform the following operations: "ADD, SUB, NAND, XOR, SHL (shift left), and SHRA (shift right arithmetic)".
The description for the ALU is provided in the 'part03_alu.pdf' file. It gives a description of the needed functionality and naming conventions. The final report is given as 'group17_part03_report.pdf'. This file gives a description of our design process, the design schematic, and a rundown of our testing methods. |
Part 3 Files
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Part 4: Single Cycle ProcessorThe fourth stage of the project was to put together everything that we had done previously, and create a single cycle processor. This processor has the ability to do all of the operations listed in '', which constitutes a complete instruction set.
The description for the processor is provided in the 'part04_singlecycle.pdf' file. It gives a description of the needed functionality and naming conventions. The final report is given as 'group17_part04_report.pdf'. This file gives a description of our design process, the design schematic, and a rundown of our testing methods. |
Part 4 Files
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Part 5: Pipelined ProcessorThe final stage of the project was to modify the single cycle processor, and turn it into a pipelined data path with hazard detection and forwarding. This part of the project was very difficult, and took a great deal of time to create a design that would function efficiently as well as effectively.
The description for the pipelined processor is provided in the 'part05_pipelined.pdf' file. It gives a description of the needed functionality and naming conventions. The control table and final running times for individual instructions are given as 'control_table_and_timing.pdf'. |
Part 5 Files
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